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24LC21
7.0
READ OPERATION
7.3
Sequential Read
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to ‘ 1 ’. There are three basic types
of read operations: current address read, random read
and sequential read.
Sequential reads are initiated in the same way as a
random read except that after the 24LC21 transmits the
first data byte, the master issues an acknowledge as
opposed to a Stop condition in a random read. This
directs the 24LC21 to transmit the next sequentially
addressed 8-bit word (see Figure 7-3).
7.1
Current Address Read
To provide sequential reads the 24LC21 contains an
The 24LC21 contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
7.4
Noise Protection
the slave address with R/W bit set to ‘ 1 ’, the 24LC21
issues an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a Stop condition and the 24LC21
discontinues transmission (Figure 7-1).
The 24LC21 employs a V CC threshold detector circuit
which disables the internal erase/write logic if the V CC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
7.2
Random Read
proper device operation even on a noisy bus.
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC21 as part of a write operation. After the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then t h e master issues the control byte again but
with the R/W bit set to a ‘ 1 ’. The 24LC21 will then issue
an acknowledge and transmits the eight bit data word.
The master will not acknowledge the transfer but does
generate a Stop condition and the 24LC21
discontinues transmission (Figure 7-2).
FIGURE 7-1:
CURRENT ADDRESS READ
S
BUS ACTIVITY
MASTER
T
A
R
Control
Byte
Data (n)
S
T
O
T
P
SDA LINE
BUS ACTIVITY
? 2004 Microchip Technology Inc.
S
A
C
K
N
O
A
C
K
P
DS21095J-page 11
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